1. Field of the Invention
The present invention relates generally to a method of fabricating memory devices and, more particularly, to a method of fabricating a memory device having a self-aligned contact.
2. Description of Related Art
Flash memories are a growing class of non-volatile storage integrated circuits. Flash memories have the capability of electrically erasing, programming or reading a memory cell in the chip. The memory cells in a flash memory are formed using so-called floating gate transistors in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically made of polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide or other insulating material, and insulated from the control gate or word line of the transistor by a second layer of insulating material.
The act of charging the floating gate is generally termed the “program” step for a flash memory. This is accomplished through so-called hot electron injection by establishing a large positive voltage between the gate and source, as much as twelve volts, and a positive voltage between the drain and source, such as, for instance, seven volts.
The act of discharging the floating gate is called the “erase” function for a flash memory. This erase function is typically carried out by a F-N tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase). For instance, a source erase operation is induced by establishing a large positive voltage from the source to gate, while floating the drain of the respective memory cell. This positive voltage can be as much as twelve volts.
Currently, contactless array non-volatile memory designs are in increasing demand. The contactless arrays include an array of storage cells which are coupled to one another by buried diffusion, and the buried diffusion is only periodically coupled through contacts to a metal bit line. Earlier flash memory designs require a “half” metal contact for each memory cell. Because metal contacts use a significant area on an integrated circuit, they can be a major impediment to creating a high density memory technology. Furthermore, as the devices become smaller and smaller, the area reduction becomes limited by the metal over contact pitches of adjacent drain and source bit lines used to access the storage cells in the array.
A need thus exists in the prior art to eliminate the bottle neck of cell shrinkage, eliminate contact photo register, and/or solve the random defect induced single bit failure problem. A further need exists to develop a method of fabricating a memory device having a self-aligned contact.